This invention relates to the design and fabrication of large scale integration (LSI) and very large scale integration (VLSI) circuit chips, and more particularly to the exposure of the circuit patterns of the chip with an automated high-speed electron beam exposure system as a step in chip fabrication. Even more particularly, the invention relates to a process whereby overlapping circuit patterns are merged automatically into one pattern, thus avoiding double exposures by the electron beam system.
When an integrated circuit chip is fabricated, it is one of many chips on a thin wafer of semiconductor material. Prior to each step in the fabrication process, the wafer is coated with a thin layer of an energy-sensitive material called "resist." The resist is then exposed, by one of a variety of techniques, with the circuit pattern corresponding to the next step of the fabrication process. The resist is then developed, uncovering those areas of the wafer that are to be subjected to the next step of the process and protecting those ares that are not to be affected. When all the steps of the fabrication process are completed, the wafer is scribed along the unused channels between the chips and the individual chips are broken off from the wafer.
As the integrated/technology evolved to what is now called LSI and VLSI, the dimensions of the individual circuits on a chip decreased, and the density, or number of circuits per unit area, increased. This requires that the circuit patterns used for each step be made more precisely for accurate alignment. The high resolution of an electron beam system makes it a good tool for exposing the circuit pattern and is commonly used in LSI and VLSI technology.
When an electron beam system is used to expose the circuit pattern, there are two basic ways in which the exposure can be made: (1) exposure of the circuit pattern directly on the resist coated wafer; and (2) creation of a mask by exposing the circuit pattern on a resist coated glass plate. When the mask method is used, the pattern on the mask is then transferred, by a variety of methods, to the resist coated wafer. Since the actual method of exposing the circuit pattern on the wafer is immaterial to the present invention, the discussion of the invention will assume the mask method is used.
The number of circuits involved in LSI and VLSI technology, coupled with the task of interconnecting this large number of circuits, virtually requires that a computer be used as a tool in LSI and VLSI design. Typically, special purpose programs are written to handle the large amount of data necessary to describe the design.
Each process step in the fabrication of a chip requires a different mask. For convenience, the masks are assigned consecutive layer numbers. The data describing the chip design is also divided into layers, processed by the programs, and output to an electron beam system to generate the masks.
Even though each company involved in the manufacture of LSI and VLSI chips usually develops programs to meet their particular needs, a very general description of the programs used can be made. In general, a chip design consists of a number of circuit designs that are interconnected to perform the desired function. The types of circuit designs used are those that will perform the logic function of the chip, circuits for receiving signals from sources external to the chip, circuits for sending signals to loads external to the chip, special circuits used to test the chip, etc.
The electron beam exposure system is a rectilinear system, that is, the electron beam itself and the stage that moves the glass plate under the electron beam both move in an XY coordinate system. Thus each layer consists of a pattern of rectangular shapes. Even a line may be described as a rectangle with a length and a finite width.
The first step in the design of a chip is to define the design of the circuits to the program. This description consists of the location of the rectangular shapes required. The description describes the basic elements of the circuit, i.e., transistors, diodes, resistors, etc. An attempt is usually made to keep the number of circuit types to a minimum. This reduces the amount of data that the programs must handle and helps control the electrical parameters of the chip. The ideal chip design would theoretically have one very general purpose circuit which could be interconnected in a large number of ways to perform all the functions desired.
The programs used give the designer the capability to place the circuits within the area of the chip, usually in some predetermined grid. The programs keep track of the locations of the rectangles that describe the design, grouped according to the layers on which they will be exposed. Once all the circuits are placed, additional programs assist the designer in interconnecting the circuits to form logic cells and in interconnecting the cells to cause the chip to perform the desired logic function.
When the overall design is complete, the programs process the data to put it in the format required to control the electron beam system. When a mask is made, the processed data (describing the rectangles that make up the circuit pattern of the layers) is output by the program to the electron beam system.
The electron beam is deflected over the area of a rectangle to expose it. As the beam is deflected, electrons scatter from the surface and some strike adjacent resist, partially exposing it. This effect, called the proximity effect, is well known and the type of resist, its thickness on the glass plate, and the rate at which the electron beam is deflected are all chosen such that the scattered electrons will not cause the adjacent resist to become totally exposed.
If two or more rectangles being exposed are overlapped or partially overlapped, the composite shape may "balloon" at the edges where the overlap occurs. This is because as each of the rectangles are exposed, the scattered electrons partially expose the resist around each rectangle. At the edges of the rectangles where they overlap, the partial exposures caused by the scattered electrons add to each other and can cause a complete exposure. The same effect will occur where two rectangles abut. The end result is that when the glass plate is developed after exposure, the shape is distorted, or ballooned, in the region of the overlap. Since the dimensions of some of the rectangles are very small, the ballooning can cause significant effects which were not anticipated in the design.
In the design of complementary metal oxide semiconductor (CMOS) circuits, it may be desirable to overlap the shapes that comprise a design. This might be done by overlapping portions of the circuits when they are placed on the chip surface by the designer to perform functions that the individual circuits alone can not perform or by overlapping portions of a circuit to insure its manufacturability. Without the present invention, to create such an overlap, the designer must define a new composite shape to the program. This adds to the complexity of the chip design by causing more circuits to be designed and more data to be handled by the program.
The present invention allows a designer to overlap circuit shapes in any manner necessary to achieve the desired function using a small set of standard circuits. When the data describing the design is processed, the present invention identifies which overlapping rectangles can be merged and determines where the overlapping region is located. It then merges the overlapping regions such that when the data is sent to the electron beam system, there will be no overlapping and no ballooning in areas where it is undesirable, leaving the area scanned substantially equivalent to that described by the original rectangles. Thus, the merging eliminates overlapping or abutting regions without modifying the pattern scanned onto the workpiece.